This tutorial show how to implement a decision-tree-based impulse noise detector to detect the noisy pixels, and an edge-preserving filter to reconstruct the intensity values of noisy pixels (”ieeexplore.ieee.org/iel5/12/6471716/06122015.pdf”) on Max10 soc . We use standard 256×256 test images to validate the design on Hardware. The images used for simulation have the resolution of 512×512 however we use 256×256 images for hardware verification because of the on-chip memory limitation. The input image to be processed is first converted into text image and stored in the on-chip RAM available on MAX10 FPGA. The processed output image (256×256) is displayed on 800×480 LCD connected to the evaluation kit at a frame rate of 60Hz.
Hardware and Software requirements
This tutorial requires you to have the following software:
■ Altera Quartus II software version 15.1 or later—The software must be installed on
a Windows or Linux computer that meets the Quartus II minimum requirements.
■ MAX10 Nios II Embedded Evaluation Kit.
Design Flow
The design flow of the project is depicted below.
InputROM : This ROM stores the text version of the input image (Pixel values of input image).
ROM configuration is as follows.
- 8 bit Data width & 64KB in depth. The depth is chosen in such a way that the ROM can store one entire frame of the input image which has 256×256 resolution.
- Read clock frequency is 33 MHz. We have chosen this frequency because LCD display is operating at a pixel clock of 33 MHz.
InputGlueLogic : This logic reads the pixel data from input ROM and send it to the noise detection module (DTBDMTop). It is operating at 33 MHz. This is responsible for implementing read interface for Input ROM.
DTBDMTop : DTBDM consists of two components: decision-tree-based impulse detector and edge-preserving image filter. The detector determines whether pi;j is a noisy pixel by using the decision tree and the correlation between pixel pi;j and its neighboring pixels. If the result is positive, edgepreserving image filter based on direction-oriented filter
generates the reconstructed value. Otherwise, the value will be kept unchanged.
OutputRAM : This RAM is instantiated to buffer the processed image which in tern displayed on the LCD graphic display.
Output RAM configuration is as follows.
- 8 bit Data width & 64KB in depth.
- Read/Write clock frequency is 33 MHz. We have chosen this frequency because LCD display is operating at a pixel clock of 33 MHz.
VGAFrameConstructor: This module is responsible for generating the appropriate VGA frame timings (Hsync & Vsync) for LCD display. It reads pixel data from Output RAM and send it to the LCD display along with Hsync & Vsync. This module operates at 33 MHz.
Video Graphics Array (VGA) Interface.
The LCD driver on Neek board (the chip that takes in video signals and translates them into what the LCD needs) accepts standard VGA signals (the same signals that would be used to drive a monitor) for sending pixel data, as well as an extra signal for enabling and disabling the backlight (MTL2_BL_ON_n). The VGA interface consists of three 8-bit signals for each of the color values (red, green, and blue) along with two synchronization signals (which tell the monitor when to update the screen). The synchronization signals require exact timing to make sure the display is drawing the correct pixels at the correct time (in essence, determining the resolution of the display).
Figure below shows the timing parameters for the common 640×480 resolution.. For the 640×480 resolution, the pixel clock would have a frequency of 25.175MHz however it is 33 MHz for 800×480 resolution. This would be the frequency you would run your VGA controller at within your FPGA..
Each line of pixels (640 pixels in this case) is ended with a horizontal synchronization pulse (active low in this case). There is a certain period of time before and after the synchronization pulse that is called the “blanking” period where the screen doesn’t display any video data. This was used in older CRT monitors to give the electron beams time to move back to the beginning of the next line and has been carried over into modern electronics for backwards compatibility. The blanking time in front of the sync pulse is called the “front porch” while the blanking time after the pulse is called the “back porch.” During the blanking period it is recommended to drive all of the color signals to zero (aka, black) to make sure nothing is displayed.
As for actual video data, each pixel clock cycle after the blanking period a new pixel will be clocked “into” the screen with the screen displaying pixel 0 in the top left corner and moving to the right to fill the line. Once the line is complete, the blanking period begins and the video data is driven low and the cycle repeats itself. In essence, for each line of data, the following is occurring (all of the timing parameters below are values you can find in the VESA standard online):
- Pixel data is shifted out over 640 clock cycles (each clock cycle determining the color for a different pixel in the line, starting on the left and moving right).
- The blanking period begins (the front porch) and video data is driven low for 16 clock cycles
- The horizontal synchronization pulse is driven low for 96 cycles. This is still part of the blanking period, so we continue to drive the video data low (aka, black).
- The horizontal synchronization pulse goes back to being asserted, and we wait 48 clock cycles for the back porch before we repeat the process and start producing pixels for the next line (moving down the screen as it goes).
The process above repeats for 480 times to display an entire frame of video data. Just as there is a blanking period after displaying an entire line of video data, there is also a blanking period after displaying an entire frame. This was used by CRT monitors to move the electron beams back to the top left corner of the screen. And just as with the horizontal timing, the blanking period consists of a front porch, synchronization pulse, and back porch where each of these parameters is measured in “lines” (how many horizontal lines it takes to fulfill that part of the blanking period). And since this is a blanking period, the video data should be driven low. The process to display an entire frame of information is shown below:
- Follow the process for displaying a single line of data above and repeat it 480 times.
- The vertical blanking period begins (front porch) and the video data is driven low for 10 lines (each one of these lines is exactly the same as the lines produced before, except the video data is always low).
- The vertical synchronization pulse is driven low for two lines.
- The vertical synchronization pulse is re-asserted and we wait 33 lines for the back porch before we start repeating the process to display the next frame of data.
Each line of video data actually takes up 800 clock cycles (640 for the visible area + 160 for the blanking period) and each entire frame of video data takes 525 lines (480 for the visible area + 45 for the blanking period).
LCD Timing Parameters
The NEEK board’s LCD follows the same VGA interface described above, albeit with different timing parameters than those described in the previous section. Perhaps, the NEEK’s LCD doesn’t use a standard resolution; it instead opts for a non-standard 800×480 resolution. Below are the timing parameters required to display data on the NEEK’s LCD:
Pixel Clock Frequency: 33MHz
VGAFramconstructor module is responsible for generating above timings to drive LCD display connected to the neek board.
Design Files.
Demonstration Setup
- Please make sure Quartus II is installed on the host PC.
- Connect the NEEK10 board (J8) to the host PC with USB cable and install the USB-Blaster II
driver. - Plug in the 5V adapter to the NEEK10 Board and power it up.
- Program DTBDM.pof /DTBDM.sof located in /Project/output_files directory of the project repository shared above.
- Push SW[0] to off position (Logic 0) to enable image processing.
- Once SW[0] is set to ‘0’ processed noise free output image is displayed on the LCD as shown in the result section.
Result.
VLSI-Design 
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