Category: RTL Design and Verification
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Low Power Design and UPF Flow in IC Design.
First, let’s discuss the different types of power components in a system, the need for low power design, and different power saving techniques before discussing UPF and the Low Power Design flow. The objective of low-power design is to reduce the total power consumed as much as possible by reducing both static & dynamic power…
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RDC in ASIC design
We shall discuss the following topics in this blog. RDC:- As the name suggests, RDC stands for “reset domain crossing“. It checks for reset ordering that could result in metastability. RDC is not for catching the missing “resets synchronizes“, but rather detecting all the meta-stability prone reset assertion order in a design that has multiple reset sources. Let’s…
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Importance of lint in ASIC design.
What is lint? Lint is a tool or a methodology that provides an insight of the RTL code at the early stage of a design. It also suggests best code and design practices. We can say lint is a virtual RTL code reviewer. It checks two key rules. Some critical checks performed by the Lint…
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Simulation Race conditions (How VHDL is race free language)
What is Race in the context of HDL simulation?. Race means same HDL code exhibiting two or more possible behaviors, both of which are correct as per the language interpretation. So, a race implies ambiguity. By its definition, race implies that there could be multiple interpretations of the same HDL, and, all of them are…
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Synchronous Resets? Asynchronous Resets?
Synchronous reset flip-flops with non reset follower flip-flops A designer should not mix resetable flip-flops with follower flip-flops (flops with no resets). Follower flip-flops are flipflops that are simple data shift registers. In the Example_1 Verilog code, a flip-flop is used to capture data and then its output is passed through a follower flip-flop. The…
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RTL coding styles that leads to pre- and post-synthesis simulation mismatch
Incomplete Sensitivity List Let us consider an example which has the incomplete sensitivity list. module Examp1 (o, a, b); output o; input a, b; reg o; always @(a) o = a & b; endmodule module Examp2 (o, a, b); output o; input a, b; reg o; always @(a, b) o = a & b; endmodule…
VLSI-Design 